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Microwave Synthesizer Design Concepts |
| Synthesizers and signal
generators are widely utilized in microwave test & measurement,
communication and defense systems. The most recognized synthesizer
architectures are phase looked loop (PLL), direct digital and direct
analog. Direct analog is very cumbersome, expensive and will not
be addressed here. We will address different aspects of PLL and DDS synthesizer design concepts as outlined below. The data presented at the bottom of the page is actual test data from product data sheets. Please take the time to review all material. • PLL Synthesizer Concepts • Direct Digital Synthesizer Concepts • Synthesizer Test Data & Comparisons |
| PLL Synthesizer Concepts The phase locked loop (PLL) is the most widely used synthesizer architecture. There are numerous PLL architectures, including single loop, self offset loop and multiple loop synthesizers, each having an almost infinite number of design-versus-performance variations. Presently, VCO based PLL synthesizers are used when switching speed is important, while yttrium iron garnet (YIG) provides superior phase noise performance. Below are very simple examples of various PLL synthesizer architectures. These block diagrams are presented to provide a conceptual understanding and do not reflect design complexity, nor the details of circuit elements (i.e. tank circuit, phase detector/comparator, ect.). |
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Single Loop PLL The VCO output is divided down in frequency, filtered to remove (most) noise and compared to a reference oscillator using a phase detector. The output of the phase comparator is essentially a DC signal used to control the VCO. This is the simplest of PLL architectures, yet it has almost infinite design variations including the choice of active device, tuning element, division ratio, phase detector and loop filter bandwidth (loop bandwidth greatly influences tuning speed and phase noise). The PLL step sized can be reduced/modified by placing a divider at the reference oscillator output. A divider at the PLL synthesizer output (fout) is sometimes used to manipulate final frequency. Synthesizer complexity increases with the number of PLL loops. |
Self Offset PLL The self offset PLL is a variation of the single loop PLL synthesizer used to reduce phase noise by reducing the PLL division ratio (÷N). PLL loop phase noise is directly related to the loop division ratio and is expressed by 20 log (N). Hence, reducing "N" will reduce phase noise. The self offset PLL splits the sampled output of the VCO, divides the two signals by predetermined offset ratios and then mix the two signals down to the phase comparator input frequency. Using the mixer to down convert the sample frequency reduces the required division ratio (÷N) and thus reduces the loop phase noise. This self offset technique reduces phase noise, but does not address other performance restrictions of single loop architecture. |
Dual Loop PLL The dual loop synthesizer is utilized in today's high performance test & measurement, communications and defense systems. The first PLL loop is essentially a single loop synthesizer that provides course tuning. The first loop (LPF) bandwidth is high, facilitating fast tuning speed. The second loop facilitates small step size and improved spectral purity. The above example has 1 MHz step size. Replacing the ÷100 divider with a programmable divider provides more step size flexibility. Improving the second loop phase noise requires reducing the loop (LPF) bandwidth at the cost of tuning speed. There is an "art" to the tuning speed versus phase noise trade-off. Experienced PLL designers use various "tricks" to maximize phase noise and tuning speed performance. |
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Direct Digital Synthesizer Concepts Recent improvements in DDS, FPGA and digital-to-analog (DAC) technology has facilitated relatively simple designs of wideband direct digital microwave synthesizers and signal generators. They have RF specifications comparable to PLL VCO based synthesizers/signal generators, but can offer significantly better switching speeds (nanoseconds versus microseconds). In the future, DDS/DAC frequencies will increase, noise floors will be lowered and process speeds and capabilities will be improved. Spectral purity of the DDS/DAC RF fundamental output is limited to the first Nyquist Zone (~40% of clock frequency). The AMD AD9914 used in the DDS synthesizer example below has a fundamental RF output of ~1.5 GHz with the reference clock speed @ 3.5 GHz. In the future, direct digital synthesis will replace PLL architectures, starting in the lower frequencies and slowing moving into microwave. Below are a few examples of DDS/DAC microwave signal generation today. These block diagrams are presented to provide a conceptual understanding and do not reflect design complexity. |
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DDS synthesizer The DDS output is multiplied up, then filtered using a switch/multiplier/filter matrix. The result is a 0.1-6 GHz synthesizer with RF performance comparable to a VCO PLL based synthesizer. Unfortunately, this design does not realize it's full potential, as the combination of the switch matrix control DSP and the DDS internal DSP slow the switching speed to ~100 uSec (versus the DDS alone @ <250 nSec) and increases the BOM cost. This synthesizer is in production; a more detailed analysis and comparison to PLL RF performance is provided below. |
FPGA->DAC synthesizer This design essentially replaces the DDS internal control core and DAC with separate FPGA control and comparable DAC. The FPGA has additional registers to control non-DDS functions such as the switch/multiplier/filter matrix. In this case, the result is a direct digital synthesizer with RF performance similar to the DDS synthesizer described on the left, but with switching speeds of <250 nSec. Additional FPGA control registers could also control other functions of a higher assembly. Although this FPGA->DAC approach requires significant upfront development, in many applications, the long term benefits justify the investment. Future performance improvement and cost reduction of FPGA and DAC technology will make this a standard design approach. Expect to see DDS manufacturers adapting this technology. |
DDS up-conversion
synthesizer The DDS output is up-converted (usually to X or Ku band) using a fixed frequency oscillator and mixer. Care must be taken to avoid mixer spurious. The result is a clean, very fast (<250 nSec), narrow band synthesizer in X or Ku band. The DDS modulation capabilities make this architecture ideal for transmitter applications. |
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| Synthesizer Test Data & Comparisons | ||||
| The data presented below was obtained from data sheets. The comparison graph was generated in Excel using the data provided. | ||||
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| This is a graph of residual phase noise of the DDS output. Residual phase noise has external influences (i.e. reference oscillator) normalized out. | This is the actual measured phase noise of the DDS based synthesizer as described above. Note that at >1 kHz offset the phase noise tracks the DDS. This indicates that the reference oscillator phase noise dominates < 1 kHz offset. | |||
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| This is the actual measured data of a very popular PLL VCO synthesizer. Notice the lack of "loop hump" and very impressive noise floor. | This is an Excel chart of data taken from the above (DDS) and left (PLL) phase noise graphs. 1.6 dB was added to the PLL 5 GHz data to extrapolate to 6 GHz. Note that below 1 kHz offset the DDS phase noise is significantly better than the PLL, and between 1 kHz and 3 MHz offset the DDS phase noise is comparable, if not better than the VCO PLL. Beyond 3 MHz offset the VCO noise drops below the DDS noise. |